Dynamic random access memory device

Details Dynamic random access memory device Dynamic random access memory device

1997-01-22

1998-08-11

Nelms, David C.

Static information storage and retrieval

Interconnection arrangements

Transistors or diodes

365 51, 365 63, 365226, G11C 506

Patent

active

057936641

ABSTRACT:
In a memory in which a memory cell array 200 and a subword drive circuit SWD are alternately arranged in a row direction in addition to an SA array 170 and a cross portion (SWC) alternately arranged, there are arranged an interface circuit 100 between a global I/O line GIOT/B and a local I/O line LIOT/B in a first cross portion SWD1, nMOSs Q2, Q4, and Q5of an SA control circuit in a second cross portion SWC2, and pMOSs Q1 and Q3 of the SA control circuit in a third cross portion SWC3.

REFERENCES:
patent: 5535153 (1996-07-01), Saeki
"A 29ns 64Mb DRAM with Hierarchical Array Architecture" Nakamura et al 1995 IEEE International Solid-State Circuits Conference; pp. 246-247.

Affiliated with

Also associated with

Rating

Dynamic random access memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic random access memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic random access memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-396190