Dynamic random access memory controller with multiple independen

Details Dynamic random access memory controller with multiple independen Dynamic random access memory controller with multiple independen

1986-05-12

1989-01-10

Gruber, Felix D.

Boots, shoes, and leggings

365222, G06F 900, G11C 1900

Patent

active

047978503

ABSTRACT:
In a data processing system, a DRAM controller which is incorporated on a single semiconductor chip employs multiple column address strobe input signals that drive multiple column address strobe output signals respectively. The multiple signal channels for the column address strobe input signal and the column address strobe output signals are independent of each other and are each connected to a plurality of memory banks, but to different byte sections of the memory. Direct access to an individual byte of word-wide data is made possible.

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patent: 4639890 (1987-01-01), Heiluril et al.
patent: 4649511 (1987-03-01), Gdula
patent: 4654804 (1987-03-01), Thaden et al.
patent: 4663735 (1987-05-01), Novak et al.
patent: 4665495 (1987-05-01), Thaden

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