Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
1999-03-24
2001-03-20
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S391000, C438S239000, C438S243000, C438S248000
Reexamination Certificate
active
06204140
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductors and more particularly to dynamic random access memories (DRAMs).
As is known in the art, DRAMs are made of storage cells having two main components: a storage capacitor; and, a transistor for enabling the transfer of charge to and from the capacitor. In trench type DRAMs, the capacitor is located in a deep trench which is etched into a semiconductor substrate. More particularly, the trench has a conductive material which provides a first electrode (i.e., sometimes referred to a the storage node) for the capacitor. The trench has a dielectric on its walls which provides the dielectric for the capacitor. A doped region in the substrate provides the second electrode for the capacitor. The first electrode is coupled to one of the source/drain regions of the cell's transistor through a coupling region formed in the semiconductor between an upper portion of the conductive region and a buried strap formed in the substrate.
Conventional DRAM arrays are organized so that multiple storage cells are positioned as close as possible to one another. In order to operate properly, it is essential that the transistor of one cell be electrically isolated from the transistor of an adjacent cell. These transistors are formed in active areas of the semiconductor substrate. These active areas are defined by a masking and etching process. One such process is sometimes referred to as shallow trench isolation (STI). More particularly, as described in U.S. Pat. No. 5,717,628 entitled Nitride Cap Formation in DRAM Capacitors, issued Feb. 10, 1998, after forming the trench capacitor, a vertical area is etched into the electrically active silicon substrate and filled with oxide. This etching of the vertical area is typically performed using a mask which must be properly aligned with the trench capacitor. More particularly, as the mask becomes positioned closer to the transistor region, the resistance of the coupling region increases; whereas if the mask becomes positioned further from the transistor region of the cell, the likelihood that the active areas of two adjacent cells becoming electrically connected to one capacitor increases.
SUMMARY OF THE INVENTION
In accordance with the invention, a method is provided including forming a trench capacitor in a semiconductor body. A recess is formed in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body. A first material is deposited over the sidewalls and over a bottom of the recess. A second material is deposited over the first material. A mask is provided over the second material, such mask having: a masking region to cover one portion of said recess bottom; and a window over another portion of said recess bottom and over a portion of said recess sidewall, to expose underlying portions of the second material. Portions of the exposed underlying portions of the second material are removed while leaving substantially un-etched exposed underlying portions of the first material. The exposed portions of the first material and underlying portions of the semiconductor body are removed. An isolation region is formed in the removed portions of the semiconductor body.
With such method, greater mask misalignment tolerances are permissible without corresponding changes in the length, and therefore the resistance, of a coupling region in the storage node of the capacitor which is electrically connected to the cell transistor through the coupling region. Further, greater mask misalignment tolerances are permissible while forming electrical isolated active areas.
In accordance with one embodiment of the invention, the mask is provided over the second material with a masking region covering one portion of said recess sidewall and one portion of said recess bottom and with a window disposed over an opposite portion of said recess sidewall and an opposite portion of said recess bottom to expose underlying portions of the second material.
In accordance with another embodiment of the invention, etching is provided into the exposed underlying portions of the semiconductor body to form a shallow trench in the semiconductor body; and, an insulating material is formed in the shallow trench to form a shallow trench isolation region.
REFERENCES:
patent: 5360758 (1994-11-01), Bronner et al.
patent: 5661320 (1997-08-01), Moriya
patent: 5717628 (1998-02-01), Hammerl et al.
patent: 5844266 (1998-12-01), Stengl et al.
patent: 6037210 (2000-03-01), Leas
patent: 6066526 (2000-05-01), Hakey et al.
patent: 6074909 (2000-06-01), Gruening
Beintner Jochen
Gruening Ulrike
Halle Scott
Mandelman Jack A.
Radens Carl J.
Braden Stanton C.
Infineon Technologies North America Corp.
Meier Stephen D.
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