Dynamic random access memory

Details Dynamic random access memory Dynamic random access memory

1990-08-01

1991-12-31

Fears, Terrell W.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365233A, G11C 1300

Patent

active

050776932

ABSTRACT:
A DRAM is operated based upon an external clock input, a column enable, and a row enable. The DRAM is accessed and row and column addresses are latched into buffers based upon the clock input.

REFERENCES:
patent: 4649511 (1987-03-01), Gdula
patent: 4710902 (1987-12-01), Pelley, III et al.
patent: 4734880 (1988-03-01), Collins
patent: 4740921 (1988-04-01), Lewandowski et al.
patent: 4754425 (1988-06-01), Bhadriraju
patent: 4823322 (1989-04-01), Miyatake et al.
patent: 4831597 (1989-05-01), Fuse
Motorola Semiconductor Technical Data, MCM514256A, 1988.

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