Dynamic RAM refresh circuit

Details Dynamic RAM refresh circuit Dynamic RAM refresh circuit

1985-07-01

1988-02-02

Harkcom, Gary V.

Boots, shoes, and leggings

365222, G06F 1300, G11C 1300

Patent

active

047232048

ABSTRACT:
A dynamic RAM refresh circuit provides the interface for timely refresh of up to 64K of RAM memory while simultaneously providing for minimal disruption of a CPU's access of that RAM memory. Circuitry is also provided to permit interlock control for timeshared access of the RAM memory on a shared basis with the refresh circuit.

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C. E. Boyd et al. "Software/Hardware Approach to Dynamic Memory Refresh," IBM Technical Disclosure Bulletin, vol. 24, No. 10, Mar. 1982.
J. M. Higdon et al. "Refresh Control for Dynamic RAM", IBM Technical Disclosure Bulletin, vol. 24, No. 10, Mar. 1982.

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