Static information storage and retrieval – Addressing – Sync/clocking
Patent
1998-02-13
2000-09-05
Tran, Andrew Q.
Static information storage and retrieval
Addressing
Sync/clocking
365149, 36523006, 36523003, 36518909, 36518911, 365226, 365201, G11C 818
Patent
active
061153192
ABSTRACT:
A bootstrap circuit is provided for a word line selector for setting word lines connected with dynamic memory cells at a select level corresponding to a first voltage and a nonselect level corresponding to a second voltage. The bootstrap circuit generates a bootstrap voltage which is given a difference substantially equal to the threshold voltage of address select MOSFETs with respect to the high level of bit lines connected with the memory cells, and feeds the bootstrap voltage to the selected word lines. The bootstrap circuit is activated in synchronism with a clock signal at a timing corresponding to an action mode designated by a command in an SDRAM before a precharge action, thereby changing the select level of the word lines from the first voltage to the bootstrap voltage.
REFERENCES:
patent: 5673233 (1997-09-01), Wright et al.
patent: 5687134 (1997-11-01), Sugawara et al.
Kinoshita Yoshitaka
Nishimoto Kenji
Tanaka Hitoshi
Yanagisawa Kazumasa
Hitachi , Ltd.
Hitachi ULSI Engineering Corp.
Tran Andrew Q.
LandOfFree
Dynamic RAM having word line voltage intermittently boosted in s does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic RAM having word line voltage intermittently boosted in s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic RAM having word line voltage intermittently boosted in s will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2219558