Dynamic ram cell with trench surrounded switching element

Details Dynamic ram cell with trench surrounded switching element Dynamic ram cell with trench surrounded switching element

1987-10-19

1988-11-22

Clawson, Jr., Joseph E.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 41, 357 45, 357 54, 357 55, 357 59, 365149, H01L 2978

Patent

active

047869542

ABSTRACT:
A semiconductor memory device has a semiconductor substrate of one conductivity type in which a plurality of memory cells are formed, each of the plurality of memory cells including at least one capacitor and having a trench which is formed from one major surface of the semiconductor substrate so as to surround at least one memory cell, wherein a first insulating film having element isolation properties is formed on a bottom and most areas of side wall surfaces of the trench, a first conductive film serving as one electrode of the capacitor is formed on the side wall of the first insulating film and an exposed portion of the semiconductor substrate which is not covered with the first insulating film, a second insulating film is formed on the first conductive film, and a second conductive film serving as the other electrode of the capacitor is formed on the second insulating film.

REFERENCES:
N. Lu, "High-Capacitance D-RAM Cell Using Buried Polysilicon . . . ," IBM Tech. Discl. Bull., vol. 26, #3B, Aug. 1983, pp. 1318-1322.
"Depletion Trench Capacitor Technology for Megabit Level MOS dRAM" by T. Morie, K. Minegishi and S. Nakajima, IEEE Electron Device Letters, vol. EDL-4, No. 11, Nov. 1983.
"A Corrugated Capacitor (ell CCC) for Megabit Dynamic MOS Memories" by H. Sunami et al., IEEE Electron Device Letters, vol. EDL-4, No. 4, Apr. 1983, pp. 90-91.
"A Submicron CMOS Megabit Level RAM Technology Using Doped Face Trench Capacitor Cell" by K. Minegishi et al., reprinted from Proceedings of The IEEE International Electron Devices Meeting, Dec. 1983, pp. 319-322.

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