Dynamic ram cell with MOS trench capacitor in CMOS

Details Dynamic ram cell with MOS trench capacitor in CMOS Dynamic ram cell with MOS trench capacitor in CMOS

1986-10-21

1987-08-18

Clawson, Jr., Joseph E.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 2311, 357 51, 357 55, 357 59, 365149, H01L 2978

Patent

active

046880631

ABSTRACT:
This invention relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly, it relates to a DRAM cell wherein at least a portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The well itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment. The trench capacitor extends from the surface of the well through the well and lightly doped substrate portion into the heavily doped portion of the substrate. The electrode disposed in the trench is directly connected to the source/drain of the access transistor.

REFERENCES:
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patent: 4296429 (1981-10-01), Schroeder
patent: 4327476 (1982-05-01), Iwai et al.
patent: 4329704 (1982-05-01), Sakurai et al.
patent: 4353086 (1982-10-01), Jaccodine et al.
patent: 4397075 (1983-08-01), Fatula, Jr. et al.
patent: 4432006 (1984-02-01), Takei
patent: 4547792 (1985-10-01), Solar
"Novel High Density, Stacked Capacitor MOS RAM" by M. Koyanagi et al. Proceedings of the 10th Conference on Solid State Devices, Tokyo 1978; Japanese Journal of Applied Physics, Supplement 18-1, pp. 35-42.
"A Corrugated Capacitor (CCC) for Megabit Dynamic MOS Memories" IEEE Electron Device Letters, vol. EDL-4, No. 4 Apr. 1983, pp. 90-91 by H. Sunami et al.
"A Submicron CMOS Megabit Level Dynamic RAM Technology Using Doped Face Trench Capacitor Cell" by K. Minegishi et al., IEDM 83, Dec. 1983, pp. 319-322.
"Very Dense One-Device Memory Cell" IBM Technical Disclosure Bulletin, vol. 25, No. 2 Jul. 1982, pp. 593-596 by C. J. Jambotkar.

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