Patent
1989-03-15
1991-12-10
Wojciechowicz, Howard J.
357 234, 357 45, 357 55, 357 51, H01L 2978
Patent
active
050722697
ABSTRACT:
A semiconductor memory device includes a plurality of semiconductor pillar projections separated by grooves formed in longitudinal and transverse directions in a substrate and arranged in a matrix manner, a MOS capacitor and a MOSFET formed on side surfaces at lower and upper portions, respectively, of each pillar projection, a diffusion layer of a source or drain of each MOSFET formed in an upper end face of the pillar projection, and a bit line connected to the diffusion layer. The bit line is in contact with the upper end face of the pillar projection in a self-alignment manner.
REFERENCES:
patent: 4630088 (1986-12-01), Ogura et al.
patent: 4672410 (1987-06-01), Miura et al.
patent: 4910567 (1990-03-01), Malhi
patent: 4914739 (1990-04-01), Malhi
Kabushiki Kaisha Toshiba
Wojciechowicz Howard J.
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