Dynamic programming of bus master channels by intelligent periph

Details Dynamic programming of bus master channels by intelligent periph Dynamic programming of bus master channels by intelligent periph

1995-08-31

1998-05-12

Swann, Tod R.

395824, G06F 1314, H04J 302

Patent

active

057520763

ABSTRACT:
An controller for allowing any of a plurality of peripheral devices to dynamically program read and write operations upon a memory. A peripheral device initiates a memory operation by transmitting a plurality of packets of information to the controller which has an interface with the memory. One of the packets includes a read/write bit identifying the memory operation as a read operation or a write operation. Each of the packets is an address packet, a data packet, or a control packet. Each of the packets includes a plurality of packet type bits which identify the type of the packet. The controller has circuitry for decoding and executing the memory operation based on the packet type bits and the read/write bit. A FIFO having a multiplexed input is provided in the controller for storing packets received from the peripheral devices and data read from the memory.

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