Dynamic power regulator for controlling memory power consumption

Telecommunications – Transmitter and receiver at separate stations – With control signal

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Details

455 88, 455343, H04B 7005

Patent

active

056258925

ABSTRACT:
A dynamic power consumption reduction apparatus for reducing power consumption by temporarily delaying multiple data transfer interfaces. Data transfer interfaces are only delayed in rare circumstances where an exceptionally high number of data transfers are occurring for a period of time. The number of active data transfer interfaces is monitored, and a count value is incremented or decremented depending on the number of active data transfer interfaces. If the count value reaches a threshold value, it indicates that the number of data transfers for a predetermined period of time is exceptionally high, and therefore power consumption is high. Where the number of data transfers is high for a predetermined period of time, delays are injected into the handshake cycle to delay return of data acknowledge signals from data receivers to data transmitters. The delays are discontinued when the data transfer interface activity is reduced to a normal level. Hysteresis is provided to allow time for the power sourcing circuitry to recharge before discontinuing the delays.

REFERENCES:
patent: 5351041 (1994-09-01), Ikata et al.

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