Dynamic PLA timing circuit

Details Dynamic PLA timing circuit Dynamic PLA timing circuit

1988-06-17

1990-09-25

Yusko, Donald J.

Communications: electrical

Continuously variable indicating

With meter reading

34082587, 307465, H04Q 100

Patent

active

049596462

ABSTRACT:
A dynamic PLA timing circuit in a PLA ROM includes a first PLA line and the address section only of another PLA line. The address section of the first PLA line is connected to the true address lines and the address section of the other PLA line is connected to the complementary address lines. Shorting bars connecting the two PLA lines are formed around each pair of true and complementary address lines such that a conductive path is formed through the address sections for any address into the ROM. The data section is connected to the gates of every data transistor. However, the drains of all but one of the data transistors are not connected to their associated data line. The data line that is connected to the associated data transistor forms the output terminal of the timing circuit.

REFERENCES:
patent: 4233667 (1980-11-01), Devine et al.
patent: 4611133 (1986-09-01), Peterson et al.
patent: 4636661 (1987-01-01), Mahmud
patent: 4697105 (1987-09-01), Moy
patent: 4740721 (1988-04-01), Chung et al.
patent: 4769562 (1988-09-01), Ghisio
patent: 4794570 (1988-12-01), Rose et al.

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