Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-02-02
2001-09-18
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06292010
ABSTRACT:
This invention relates generally to driver circuits for automatic test equipment, and more particularly to driver circuits for providing stimuli to a device under test under dynamic control.
BACKGROUND OF THE INVENTION
Automatic test equipment (ATE) plays a significant role in the manufacture of semiconductor devices. Manufacturers generally use automatic test equipment, or “testers,” to verify the operation of semiconductor devices at the wafer and packaged device stages of the semiconductor manufacturing process. By verifying the operation of semiconductor devices at these stages, manufacturers are able to reject defective devices early in the manufacturing process. Early detection of faults eliminates costs that would otherwise be incurred by processing defective parts, and thus reduces the overall costs of manufacturing. Manufacturers also use ATE to grade various specifications of devices. Devices can be tested and categorized into different bins that correspond to different levels of performance in significant areas, for example, speed. Parts can then be labeled and sold according to their actual levels of performance.
The ATE, or tester, generally includes a host computer that runs software for controlling various tests of semiconductor devices. The software prescribes signal parameters for stimuli that drive the device under test (DUT), and prescribes expected data for responses to be sampled from the DUT. A pattern generator translates the signal parameters from the test software into timing signals. Specialized circuitry called pin electronics then translates the timing signals from the pattern generator into electronic stimuli to be applied to the DUT. The pin electronics also translates the timing signals into windows for sampling electronic responses from the DUT.
The pin electronics are generally grouped among a number of circuits of the ATE called “channels.” The channels perform a variety of tester functions and generally serve as a signal interface between the tester and the DUT. Each channel typically includes a driver circuit, a detector circuit, and a load. The present invention pertains to an improvement to driver circuits used in pin electronics channels of ATE.
FIG. 1
illustrates the conventional role of driver circuits in ATE systems. As shown in
FIG. 1
, an ATE system includes a host computer
118
, a pattern generator
120
, and plurality of driver circuits, shown generally as driver circuits
110
a
-
110
e
. The host computer
118
runs test software that defines tests to be executed. The pattern generator
120
converts instructions from the test software into precisely controlled, high-resolution timing signals. The channels then use the timing signals to provide precisely timed stimulus and response.
Each driver circuit
110
a
-
110
e
supplies an output signal to the DUT
124
and typically includes a first source
112
, a second source
114
, and a switching element
116
. The first source
112
generates a high voltage level VIH, and the second source
114
generates a low voltage level VIL. The voltage levels VIH and VIL typically correspond to high and low logic levels of digital circuitry within the DUT
124
. Under control of a High/Low (“H/L”) timing signal
122
from the pattern generator
120
, the switching element
116
alternately passes the output of first source
112
and the output of the second source
114
to the output of the driver circuit. In this manner, voltage levels are provided to the DUT
124
that alternate between VIH and VIL with precisely controlled timing.
Operating the ATE system of
FIG. 1
involves both static and dynamic activities. Static activities are generally not timing critical. They include, for example, programming digital-to-analog converters (DACs) for establishing values for VIH and VIL, and programming DACs or other devices for establishing clock periods and edge locations for the pattern generator
120
. In contrast, dynamic activities generally are time critical. Dynamic activities include “bursts,” waveforms that have periods and/or edge placement precisely controlled by the pattern generator. Once the ATE system has been statically programmed, an instruction from the test program starts a burst. The pattern generator
120
produces precisely timed, high-resolution signals, and the driver circuits generate stimuli in response to those timing signals.
FIGS. 2
a
and
2
b
illustrate two driver topologies of the prior art, which employ the general approach described above. In
FIG. 2
a
, a driver circuit includes a voltage buffer
210
having a complementary pair of bipolar output transistors
218
and
220
arranged in a “push-pull” configuration. The driver circuit also includes a VIH buffer
212
and a VIL buffer
214
. The voltage levels of the VIH and VIL buffers
212
and
214
are statically programmed by the host computer. In response to a dynamic H/L timing signal
226
, outputs of these buffers are dynamically switched through a multiplexor
216
to the bases of the transistors
218
and
220
. An alternating voltage then appears at the output of the voltage buffer
210
.
A transmission line
222
conveys the output of the voltage buffer
210
to a DUT
224
. The DUT
224
is terminated to a termination voltage V
DUT
. Generally, the characteristic impedance of the transmission line
222
approximately equals 50 ohms. If the impedance of the DUT
224
also equals 50-ohms, output signals from the voltage buffer
210
are transmitted to the DUT
224
without significant. Optionally, a backmatch resistor (not shown) is coupled in series with the output of the voltage buffer
210
to raise the overall output impedance of the voltage buffer
210
to 50 -ohms. If the impedance of the DUT is different from 50-ohms, the backmatch resistor terminates reflections from the DUT
224
.
FIG. 2
b
illustrates another driver topology of the prior art, which employs a current buffer
250
. The current buffer
250
includes a VIH buffer
252
, a switchable current buffer
254
, and a resistor
256
. The switchable current buffer
254
generates an output current that corresponds to either a high output current IH or a low output current IL. The host computer statically programs the VIH buffer
252
and the switchable current buffer
254
for appropriate values of VIH, IH, and IL. Once programmed, the VIH buffer maintains its statically programmed value. In response to a dynamic timing signal H/L
266
, the switchable current buffer
254
generates a current that alternates between IH and IL dynamically.
The steady-state output voltage of the driver circuit of
FIG. 2
b
results from the combined contributions of the switchable current buffer
254
, the VIH buffer
252
, the resistor
256
(assumed to be 50-ohms), a DUT
264
, and the DUT termination voltage V
DUT
. The steady-state output voltage can be expressed as follows:
V
OUT
=
50
V
DUT
+
R
DUT
V1H
-
50
R
DUT
I
IN
50
+
R
DUT
.
(
1
)
In this expression, I
IN
equals either IH or IL, depending on the state of the H/L signal
266
, and R
DUT
equals the resistance of the DUT
264
.
We have recognized a need for driver circuits that can deliver high voltage range and very high speed. We have experimented with the topologies of
FIG. 2
a
and
FIG. 2
b
and have found that neither of these circuits appears to be capable of meeting both requirements.
SUMMARY OF THE INVENTION
With the foregoing background in mind, it is an object of the invention for a driver circuit to have both high voltage range and high speed.
To achieve the foregoing object and other objectives and advantages, a driver circuit includes a voltage buffer having an output and generating an output voltage that has at least two voltage levels. The output voltage is variable between one voltage level and another voltage level in response to a first dynamic timing signal. The driver circuit also includes a current buffer having an output coupled to the output of the voltage buffer. The output current of the current buffer has at least two current levels, and is variable
Bishop Charles D.
Persons Thomas W.
Metjahic Safet
Nguyen Vincent Q.
Rubenstein Bruce D.
Teradyne, Inc.
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