Dynamic phase-locked loop circuits and methods of operation...

Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation

Reexamination Certificate

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C331S017000, C331S034000, C331SDIG002, C327S156000, C327S157000, C327S159000

Reexamination Certificate

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07046093

ABSTRACT:
A phase locked loop (PLL) circuit includes a controlled oscillator circuit that is operative to generate an output clock signal responsive to an oscillator control signal according to a plurality of selectable transfer functions, and an oscillator control signal generator circuit that is operative to generate the oscillator control signal responsive to the output clock signal and a reference clock signal. The PLL circuit further includes a transfer function control circuit operative to transition operation of the controlled oscillator from a first one of the transfer functions to a second one of the transfer functions responsive to the oscillator control signal. For example, the transfer function control circuit may step the controlled oscillator circuit through a succession of the transfer functions in response to a change in a frequency of the reference clock signal and may enable a closed loop including the oscillator control signal generator circuit and the controlled oscillator circuit upon selection of each of the succession of transfer functions.

REFERENCES:
patent: 4855689 (1989-08-01), Kinkel
patent: 5126690 (1992-06-01), Bui et al.
patent: 5408202 (1995-04-01), Shirazi et al.
patent: 5485490 (1996-01-01), Leung et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 5626325 (1997-05-01), Buchanan
patent: 5942949 (1999-08-01), Wilson et al.
patent: 5973572 (1999-10-01), Ukita
patent: 6114920 (2000-09-01), Moon et al.
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6236697 (2001-05-01), Fang
patent: 6252471 (2001-06-01), Salter et al.
patent: 6356160 (2002-03-01), Robinson et al.
patent: 6466070 (2002-10-01), Ross
patent: 6539072 (2003-03-01), Donnelly et al.
patent: 6583675 (2003-06-01), Gomez
Lee et al., “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM,” IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994, pp. 1491-1496.

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