Telecommunications – Receiver or analog modulated signal frequency converter – With wave collector
Reexamination Certificate
1999-09-14
2003-01-14
Cumming, William (Department: 2684)
Telecommunications
Receiver or analog modulated signal frequency converter
With wave collector
C375S345000
Reexamination Certificate
active
06507732
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to wireless communication systems and more specifically to gain compensation in the digital front end of a radio transmitter.
BACKGROUND OF THE INVENTION
The nature of CDMA, which requires a high peak power to average power ratio of 8 dB or higher, makes providing a linear RF path of constant gain, a difficult and costly challenge. Since base station cost is RF amplifier-centric, failure to accurately regulate the RF path either wastes amplifier power or under utilizes the amplifier capacity. The base station cost in terms of size, weight, heat, and direct current (DC) power, is directly affected by the method of regulating the RF path gain.
Furthermore, preserving the nominal path gain is important to maximizing service provider revenue and mobile service availability. If path gain is calibrated too low, the RF amplifier power overload protection acts too soon at a lower air interface call capacity, which implies lower revenue for the service provider and disappointed customers unable to obtain service on demand. For example, if due to losses, the path gain was 1 dB lower than expected, a call that would normally require a gain setting of 60 digital gain units (“dgu”) (a unit of voltage) would require 67 dgus to provide the mobile with the same signal power, measured in dgu
2
(e.g., 1.259*60
2
~=67
2
, where 1 dB~=1.259). Since the maximum power is nominally 77760 dgu
2
, about seventeen 60 dgu calls could be supported (e.g., 77760-16800 overhead~=17*60*60) where as, only about thirteen, 67 dgu calls could be supported (e.g., 77760-16800 overhead~=13*67*67). Therefore, while the system would try to support seventeen calls, it would be doing so at 67 dgu per call. The RF amplifier overload protection would kick in at about thirteen calls, supporting roughly only three quarters of the number of calls that should be supported.
If, on the other hand, path gain is calibrated too high, equipment life may be shortened and as descried below, the FCC can take regulatory action against the service provider for spectral non-compliance. Indeed, a high path gain may cause too much DC current in the power amplifier, blowing the power supply fuse and shutting down the RF path through that amplifier. A high path gain also distorts the RF coverage footprint, which increases interference to neighboring cells and lowers the network air interface capacity. This occurs because: (i) path gain is applied equally to the traffic signals and the pilot signal. The pilot signal is used by mobile stations to determine the base station they are to listen to for their signal. With high path gain, the pilot signal will be too strong, thereby attracting too much traffic away from neighboring cells; (ii) the amplifier is operated at a higher than expected power (e.g., If the RF path gain increased 1 dB higher than the nominal path gain, a 60 dgu call would only need 54 dgu to provide the mobile with the necessary power (e.g., 60
2
/ 1.259~=54
2
, where 1 dB~=1.259). The cell would therefore accept and attempt to support approximately 20 calls, as opposed to 17, before amplifier overload protection kicks in. This in turn could introduce noise and out-of-band emissions. Mobile stations would then require more signal power to overcome the noise and FCC out-of-band emission power limits could be exceeded.
Present art provides individual solutions for each constraint that affects path gain such that they generally do not account for interactions among components in the RF path. Furthermore, most of the solutions are static and non-tunable. These include: using additional semiconductor junctions to improve linearity in each amplification stage over the operational temperature range; matching component parts by selection, which requires extra steps in the manufacturing process; laser trimming of components until their properties satisfy the specifications, which also requires extra production steps; and connecting passive components with inverse thermal characteristics in series to constrain path gain variance over temperature.
Furthermore, current solutions use wide tolerance ranges for path gain, requiring larger and more costly equipment than would be required with tighter tolerances. Much control is essentially open loop, providing no feedback means for adjusting the path gain based on actual performance of the path. Rather, conservative nominal values are assigned to constraints, a priori. Manual adjustment is often required to optimize performance, which only remains optimal over a narrow temperature range.
There are also closed loop control solutions that measure input and output power and adjust the path gain to preserve the nominal gain, which is the desired ratio of output power over input power. This is done within components as well as across a plurality of components.
Accordingly, it is desirable to preserve a nominal RF path gain seamlessly and accurately by compensating for gain changes in multiple physical components, which may be non-linear, without exceeding their physical constraints and in a way that provides for performance tuning and product evolution.
SUMMARY OF THE INVENTION
A dual port RAM (“DPRAM”) is placed in the RF path at some point prior to the digital to analog converter (“DAC”), to provide dynamic path gain compensation to the digital signal prior to conversion to an analog signal. One DPRAM can be used at the output of the digital up converter (“DUC”), or separate DPRAMs, one for each of the I and Q streams may be placed in the RF stream prior to the DUC. In accordance with the present invention the DPRAM stores corrections to the signal to compensate for path gain variance, such as amplitude losses in the signal arising from heat and non-linearities.
The DPRAM acts as an ultra-fast multiplier. The DPRAM can operate at higher data rates and with a lower transport latency than conventional high-speed multipliers. The DPRAM multiplies by table lookup. In the DPRAM, the pre-calculated product of the path gain correction times the signal level is stored for each possible signal level. This offers another advantage in that the signal multiplication can be non-linear. In other words, a different gain correction can be used for each possible signal level.
The DPRAM typically comprises two blocks of RAM, although multiple blocks of RAM are possible. One block is for replacing the input signal with a multiple of the input signal, in lieu of actually multiplying the input signal on the fly. The uncorrected input signal level drives the DPRAM address lines and the corrected signal level, which is stored within one of the blocks of the DPRAM, comes out on the data lines. The other, inactive, block(s) is (are) for updating, where necessary, the next set of corrections by a controller. Thus, the dual port on the DPRAM allows one block of address space to exist in the signal stream and the other block(s) of address space to be accessible by the controller. A logic switch alternately directs an input signal to one of the blocks, which seamlessly provides the corrected signal on the data lines.
At the input interface to the DPRAM, the logic switch toggles one of the address bits, which may advantageously be the most significant bit (“MSB”) although any of the address bits may be used. Thus for any particular value being input to the DPRAM, an “off” MSB will direct the signal to one block, while an “on” MSB will direct the signal to another parallel block. Updated values are written to a first block while the input from the DUC is directed to a second block. After the updating is complete, the logic switch will cause the signal from the DUC to be input to the second block. At this point, and until the logic switch is toggled again, updates will be written to the first block. This allows all correction calculations to occur in the digital realm. The logical switch mechanism could also use multiple address lines for selecting the multiplying block and the updatable block. In particular, this would be the
Dajer Miguel
Eibling Edward Ellis
McKinnon Mark Y.
Cumming William
Lucent Technologies - Inc.
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