Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2005-11-08
2005-11-08
Peikari, B. James (Department: 2189)
Static information storage and retrieval
Addressing
Sync/clocking
C710S058000, C710S059000, C710S060000
Reexamination Certificate
active
06963516
ABSTRACT:
A method and apparatus is provided which dynamically alters SDRAM memory interface timings to provide minimum read access latencies for different types of memory accesses in a memory subsystem of a computer system. The dynamic alteration of the SDRAM memory interface timings is based on workload and is determined with information from the memory controller read queue.
REFERENCES:
patent: 5544124 (1996-08-01), Zagar et al.
patent: 6418067 (2002-07-01), Watanabe et al.
patent: 6542416 (2003-04-01), Hampel et al.
Blackmon Herman Lee
Borkenhagen John Michael
Kirscht Joseph Allen
Marcella James Anthony
Shedivy David Alan
Nock James R.
Peikari B. James
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