Dynamic MOS-logic in interlace-techniques

Details Dynamic MOS-logic in interlace-techniques Dynamic MOS-logic in interlace-techniques

1981-01-08

1983-11-15

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307453, 307581, 307450, H03K 19017, H03K 19096, H03K 1920

Patent

active

044158190

ABSTRACT:
Some known logic MOS circuits operated too slowly because too many "branches" were connected to a node of the circuit to be charged or discharged for the information transfer. The invention relates to a circuit arrangement with isolated branches, so that a faster clock signal can be used, which results in faster operation of the circuit.

REFERENCES:
patent: 3573487 (1971-04-01), Polkinghorn
patent: 3852625 (1974-12-01), Kubo
patent: 3982138 (1976-09-01), Luisi et al.
patent: 4107548 (1978-08-01), Sakaba et al.
patent: 4123669 (1978-10-01), Devine et al.

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