Dynamic MOS circuit block and static bipolar transistor circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307269, 307480, 377 78, 377 79, H03K 19092, H03K 19096, G11C 1928

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045256390

ABSTRACT:
A digital semiconductor integrated circuit device comprising a common semiconductor substrate, a dynamic MOS circuit block composed mainly of a MOS-FET, and a static bipolar circuit block composed of a bipolar transistor or an SIT which is operated in a "bipolar mode" and cascade-connected to said dynamic MOS circuit block in said common semiconductor substrate, and arranged to be operative so that, by setting the timing of clock pulses, the logical operations of these circuit blocks are performed in a timed relationship with each other. Thus, this integrated circuit device can be produced with minimized dependency of its operation velocity upon the design of these circuit blocks and can perform a high-speed operation and can provide a high packing density.

REFERENCES:
patent: 3745539 (1973-07-01), Davidson et al.
patent: 3993916 (1976-11-01), Copeland et al.
patent: 4034301 (1977-07-01), Kashio
patent: 4150392 (1979-04-01), Nonaka
patent: 4398833 (1983-08-01), Tanaka
Nishizawa, "Bipolar Mode Static Induction Transistor", Proceedings 11th Conf. ISSD, Tokyo, Japan, 1979, J.J.A.P., vol. 19, (1980), pp. 289-293.

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