Dynamic merged load logic (MLL) and merged load memory (MLM)

Details Dynamic merged load logic (MLL) and merged load memory (MLM) Dynamic merged load logic (MLL) and merged load memory (MLM)

1980-12-29

1984-05-15

Larkins, William D.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular transfer means

357 23, 357 24, 357 30, 307446, 365149, H01L 2704, H01L 2978, G11C 1140

Patent

active

044492243

ABSTRACT:
MOS dynamic logic/shift registers employing as load elements either a parasitic bipolar transistor whose emitter is the drain of the MOS element, or the drain-substrate diode charged via bi-polar signals on the clock lines capacitively coupled to the drain. Uses for logic, memory, and imaging applications.

REFERENCES:
patent: 3601627 (1971-08-01), Booher
patent: 3621292 (1971-11-01), Vogel et al.
patent: 3662356 (1972-05-01), Michon et al.
patent: 3683201 (1972-08-01), Haraszti
patent: 3740576 (1973-06-01), Haraszti
patent: 3745370 (1973-07-01), Kjar
patent: 3788904 (1974-01-01), Haraszti et al.
patent: 3829710 (1974-08-01), Hirasawa et al.
patent: 4190778 (1980-02-01), Krause
patent: 4319263 (1982-03-01), Rao
patent: 4329706 (1982-05-01), Crowder et al.
Crawford, MOSFET in Circuit Design, (McGraw-Hill, N.Y., 1967) pp. 100-101, 104-105.

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