Dynamic memory with error correction on refresh

Details Dynamic memory with error correction on refresh Dynamic memory with error correction on refresh

1984-01-11

1985-01-08

Malzahn, David H.

Excavating

371 13, G06F 1110

Patent

active

044930810

ABSTRACT:
An apparatus is disclosed for error correcting during the refresh cycle of a dynamic memory. The apparatus includes a refresh counter means for supplying row addresses to a dynamic memory during refresh cycles and decoder circuitry for supplying row address and column address strobe signals to the memory to cause it to refresh rows sequentially and pick one word out of each refreshed row for error correcting.
Also disclosed is a computer system utilizing a semiconductor memory with on-board error correcting circuitry using hamming codes to generate check bits from which they are generated. Upon access of data from the memory, the check bits are used to locate and correct single bit errors and detect some double bit errors. A CPU is disclosed which incorporates a spot check system stored in non-volatile memory to independently randomly generate syndrome bits from data accessed from memory and compare these syndrome bits to the check bits stored with the accessed data. The CPU is stopped if the syndrome bits and check bits so compared are not identical.

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