Dynamic memory refresh and parity checking circuit

Details Dynamic memory refresh and parity checking circuit Dynamic memory refresh and parity checking circuit

1985-09-27

1987-07-21

Atkinson, Charles E.

Excavating

371 51, G11C 2900, G06F 1110

Patent

active

046823280

ABSTRACT:
A circuit for use in conjunction with a microprocessor for refreshing, checking and correcting data signals stored in a dynamic memory. The circuit utilizes a direct memory access controller for transferring data signals stored in successive locations of the dynamic memory to a non-existent peripheral. Data signals appearing on a data bus as a result of the data transfer, are applied to a parity checking circuit for generating an interrupt signal to the microprocessor in response to detection of parity errors in the data signal. The microprocessor then performs a data recovery routine in which correct versions of the data signal stored in a non-volatile memory, are transferred for storage in the dynamic memory under control of a microprocessor. Parity errors in data signals stored in the dynamic memory are thus corrected prior to being accessed by the microprocessor.

REFERENCES:
patent: 4183096 (1980-01-01), Cenker et al.
patent: 4355393 (1982-10-01), Kubo et al.
patent: 4380812 (1983-04-01), Ziegler, II et al.
patent: 4493081 (1985-01-01), Schmidt

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