Dynamic memory mapper which supports interleaving across 2.sup.N

Details Dynamic memory mapper which supports interleaving across 2.sup.N Dynamic memory mapper which supports interleaving across 2.sup.N

1991-03-12

1993-09-21

Dixon, Joseph L.

Boots, shoes, and leggings

395400, 364DIG1, 364229, 3642544, 364265, 3642683, 36494492, 3649572, G06F 1206, G06F 1300

Patent

active

052476456

ABSTRACT:
A memory system for a high performance data processing system comprises a plurality of memory modules. In the preferred embodiment, there are 2.sup.N +1 memory modules. In a specific example, there are 65 such modules. When all 65 modules are enabled, a real-to-physical translation unit generates logical module addresses from 0 to 64 using modulo 65 calculations. Once a module failure is detected, the translation unit maps the real addresses to logical module addresses from 0 to 63 by performing modulo 64 calculations. The contiguous set of logical module addresses are then mapped to a set of physical module addresses which do not include the failed module.

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Budnik et al., "The Organization and Use of Parallel Memories", IEEE Transactions on Computers, Dec. 1971, pp. 1566-1569.

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