Dynamic memory in integrated circuit form

Details Dynamic memory in integrated circuit form Dynamic memory in integrated circuit form

1986-02-10

1989-12-19

Tarcza, Thomas H.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 45, 357 41, 365174, H01L 2978, H01L 2710, G11C 1134, G11C 1140

Patent

active

048886289

ABSTRACT:
In a dynamic memory for capacitive data storage, enhanced storage performances are achieved by increasing the value of the storage capacitance. A junction capacitor is formed between the source region and the well region in which the memory cells are formed, the junction capacitor being associated with a conventional capacitor. By judiciously and heavily doping the wells, the junction capacitances are appreciably increased. The heavy-doping operation is performed by backward implantation of the wells at very high energy in order to place the concentration peak of the wells at the depth of the base of the thick oxides which form separations between memory cells.

REFERENCES:
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patent: 4329706 (1982-05-01), Crowder et al.
patent: 4355374 (1982-02-01), Sakai et al.
patent: 4628590 (1986-12-01), Udo et al.
Novel High Density, Stacked Capacitor MOS RAM, Koyanagi et al., Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185 Japan, pp. 348-351.
IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1982, New York, USA, pp. 714-718, "An n-well CMOS Dynamic RAM", Katsuhiro Shimohigashi et al.
"A High Density, High Performance 1T DRAM Cell", A. Mohsen et al., pp. 616-619, 1982, IEEE.
8107 IEEE Journal of solid-State Circuits, vol. SC-18 (1983), Oct. No. 5, New York, USA, pp. 457-463, "A 70 ns High Density 64K CMOS Dynamic RAM", Ronald J. C. Chwang et al.

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