Dynamic memory diagnosis and error correction apparatus

Details Dynamic memory diagnosis and error correction apparatus Dynamic memory diagnosis and error correction apparatus

1985-07-29

1987-09-15

Fleming, Michael R.

Excavating

371 38, 365 22, G11C 700

Patent

active

046944540

ABSTRACT:
In a certain refresh cycle, a certain address is designated as a refresh address, and a read operation for the refresh is conducted. The data thus read out is checked, and, if a correctable error is detected, the corrected data and its address are held in a corrected data register and an address register, respectively. In the succeeding refresh cycles, reading operations for the refresh are conducted for the succeeding addresses. When the same address as that held in the address register is designated again in due time as the refresh address, a writing operation for the refresh is conducted to write back the content of the corrected data register.

REFERENCES:
patent: 4371930 (1983-02-01), Kim
patent: 4412314 (1983-10-01), Proebsting
patent: 4535455 (1985-08-01), Peterson
patent: 4542454 (1985-09-01), Brcich
patent: 4593391 (1986-06-01), Mizushima
patent: 4604749 (1986-08-01), Shinoda
patent: 4604751 (1986-08-01), Aichelmann

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