Dynamic memory device with improved wiring layer layout

Details Dynamic memory device with improved wiring layer layout Dynamic memory device with improved wiring layer layout

1989-10-03

1990-07-10

Hille, Rolf

357 68, 357 51, 357 236, 357 71, H01L 2710, H01L 2348, H01L 2702, H01L 2978

Patent

active

049410318

ABSTRACT:
A signal line runs in parallel with first to fourth bit lines on a memory cell array of a dynamic memory device. The signal line runs between and along the first and third bit lines, turns at a predetermined position, turns again and runs between and along the second and fourth bit lines. The predetermined turning position is a position corresponding to the half of the bit line length. The result is that the stray capacitances between the signal line and these bit lines are equal at about 1/2C.sub.F.

REFERENCES:
patent: 4748597 (1988-05-01), Saito et al.
patent: 4833518 (1989-05-01), Matsuda et al.
Mano et al., Circuit Technologies for 16Mb DRAMs, IEEE International Solid State Circuits Conference, Feb. 25, 1987, pp. 22-28 & 323-324.

Affiliated with

Also associated with

Rating

Dynamic memory device with improved wiring layer layout does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic memory device with improved wiring layer layout, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic memory device with improved wiring layer layout will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1723849