Dynamic memory device having a single-crystal transistor on a tr

Details Dynamic memory device having a single-crystal transistor on a tr Dynamic memory device having a single-crystal transistor on a tr

1985-10-21

1987-03-17

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

357 236, 357 51, 29576C, 29576E, 29577C, 29580, H01L 2710, H01L 2978, G11C 1134

Patent

active

046496254

ABSTRACT:
Dynamic random access memory (DRAM) devices are taught wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor and a fabrication method therefor wherein crystallization seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2 is provided for the capacitor storage insulator. A thin layer of SiO.sub.2 is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO.sub.2 layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.

REFERENCES:
patent: 3421055 (1969-01-01), Bean et al.
patent: 4327476 (1982-05-01), Iwai et al.
patent: 4353086 (1982-10-01), Jaccodine et al.
patent: 4397075 (1983-08-01), Fatula, Jr. et al.
patent: 4462847 (1984-06-01), Thompson et al.
J. H. Douglas, `The Route to 3-D Chips`, High Technology, Sep. 1983, pp. 55-59.
Dynamic RAM Cell with Merged Drain and Storage, IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr. 1985, pp. 6694-6697.

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