Dynamic memory controller for single-chip microprocessor

Details Dynamic memory controller for single-chip microprocessor Dynamic memory controller for single-chip microprocessor

1983-07-25

1987-03-10

Thomas, James D.

Boots, shoes, and leggings

365222, 365233, G06F 1200

Patent

active

046495118

ABSTRACT:
A controller for interfacing a single-chip microcomputer with external dynamic random-access memory, includes a subcircuit for generating a column-address strobe at a time after a row-address strobe is generated, and also includes a multiplexing subcircuit for providing the proper 8-bit portion of a 16-bit address output from the microprocessor to the 8-bit dynamic memory inputs, prior to receipt of the associated row-address or column-address strobe. The microprocessor utilizes the strobe-generation and multiplexing subcircuits to burst-refresh the dynamic memory, in one presently preferred embodiment. In another presently preferred embodiment, lines from an additional microprocessor output port are utilized with a resettable binary counter and a multiplicity of buffers, to count through the range of row addresses in cyclic fashion, with each address being incremented after the previously-addressed row of memory cells has been refreshed.

REFERENCES:
patent: 4153933 (1979-05-01), Blume, Jr.
patent: 4249247 (1981-02-01), Patel
patent: 4328566 (1982-05-01), Thaler

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