Patent
1985-06-04
1987-08-18
Edlow, Martin H.
357 41, 357 55, 357 52, H01L 2978, H01L 2702, H01L 2906, H01L 2934
Patent
active
046880640
ABSTRACT:
A first semiconductor layer of a P.sup.+ type is formed on a semiconductor substrate of a P.sup.- type and a mask layer is formed on a portion of the first semiconductor layer other than that area where a capacitor is to be formed. A hole is formed in a direction of a thickness of the first semiconductor layer, using the mask layer. An N.sup.+ layer is formed on the inner surface of the hole with the mask layer as a mask. An insulating film for capacitor formation is formed on the inner surface of the resultant hole and on that area of the first semiconductor layer where the resultant dynamic memory cell is electrically separated from an adjacent dynamic memory cell. A conductive layer acting as a capacitor electrode is formed on the capacitor formation insulating film. With the conductive layer as a mask, an impurity of an N type is doped into the first semiconductor layer to form a second semiconductor layer of a P.sup.- type in the surface portion of the first semiconductor layer. A MOS transistor is formed in the surface portion of the second conductive layer.
REFERENCES:
patent: 4538166 (1985-08-01), Nakano
patent: 4577395 (1986-03-01), Shibata
Chang T. S. IBM Technical Disclosure Bulletin vol. 22, No. 11 Apr. 1980 pp. 4929-4930.
Masuoka Fujio
Ogura Mitsugi
Edlow Martin H.
Kabushiki Kaisha Toshiba
Limanek Robert P.
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