Dynamic memory address system for I/O devices

Details Dynamic memory address system for I/O devices Dynamic memory address system for I/O devices

1981-03-18

1989-03-21

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 900

Patent

active

048150347

ABSTRACT:
Individual pieces of digital equipment such as I/O units are provided each with a connect circuit which includes a ROM containing an otherwise incomplete but device-specific, dedicated service program; and each such program portion completes a likewise incomplete program contained in a processor so that this processor can serve as a time-shared controller for each I/O unit. The system includes a common bus, and particular features relate to process inclusion of all ROM's in a common memory continuum.

REFERENCES:
patent: 3283308 (1966-11-01), Klein et al.
patent: 3699532 (1972-10-01), Schaffer et al.
patent: 3975714 (1976-08-01), Weber et al.
patent: 4086659 (1978-04-01), Cizmic et al.
patent: 4103766 (1978-08-01), Ruble et al.
patent: 4321665 (1982-03-01), Shen et al.
Motorola Microprocessors, 1981, pp. 3-455, Motorola Inc.

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