Dynamic memory address line decoding

Details Dynamic memory address line decoding Dynamic memory address line decoding

1994-02-01

1996-06-25

Elmore, Reba I.

395402, 395432, 395412, 39542101, G06F 1206

Patent

active

055309348

ABSTRACT:
An apparatus dynamically decodes memory addresses while supporting memory map options that require different memory bits which are dependent upon the memory address. A current CPU address or an address stored in an expanded memory specification (EMS) register is selected as the defining address. This defining address is then decoded by one of twenty-five (25) memory map options available. The resultant decoded signal drives select lines of a multiplexer whose output drives memory address lines to on-board banks of DRAMS.

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