Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-07-19
2008-12-16
Mai, Son L (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S185130, C365S185200
Reexamination Certificate
active
07466594
ABSTRACT:
A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier. The non-accessed global bit line may be dynamically chosen as the global bit line adjacent to the global bit line used for driving both the drains of the array and the reference cells.
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Betser Yoram
Maayan Eduardo
Sofer Yair
EMPK & Shiloh, LLP
Mai Son L
Saifun Semiconductors Ltd.
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