Dynamic logic MUX

Details Dynamic logic MUX Dynamic logic MUX

2002-06-19

2003-04-15

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

C327S200000, C327S408000

Reexamination Certificate

active

06549060

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to digital integrated electronic circuits and more particularly to a digital dynamic multiplexer (MUX).
BACKGROUND OF THE INVENTION
A multiplexer (or MUX, or data selector) has a group of control inputs that is used to select one of a group of data inputs and connect that input, or relay the value on that input, to the output terminal. MUX's have been implemented in many different logic families including static logic families and dynamic logic families. One such implementation of a dynamic logic MUX is shown in FIG.
1
.
Unfortunately, the dynamic logic MUX shown in
FIG. 1
suffers from at least one problem. Subthreshold leakage current through transistors on the nonselected inputs can cause the output to switch incorrectly. This problem is aggravated when, to increase speed, the process technology is modified to make the threshold voltage of the transistors smaller.
SUMMARY OF THE INVENTION
A dynamic logic multiplexer has pullups on its input signals that pull-up the input signals when not selected. This reduces leakage current that may contribute to incorrect switching of the output. The output stage of the multiplexer includes a latched dynamic node followed by two gain stages, and an open-drain output.


REFERENCES:
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patent: 5706323 (1998-01-01), Miller
patent: 5926487 (1999-07-01), Chappell et al.
patent: 5933038 (1999-08-01), Klass
patent: 6320794 (2001-11-01), Kang et al.
patent: 6438051 (2002-08-01), Fifield et al.
Charles M. Lee and Ellen W. Szeto, “Zipper CMOS”. IEEE Circuits and Devices Magazine, May 1986, pp. 10-17.

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