Dynamic logic circuit with reduced operating current

Details Dynamic logic circuit with reduced operating current Dynamic logic circuit with reduced operating current

1992-01-27

1993-10-05

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307463, 365203, 365204, 365239, H03K 1920, G11C 700

Patent

active

052508579

ABSTRACT:
In a dynamic logic circuit, an X decoder and a Y decoder receive a more significant bit portion and a less significant bit portion of an internal address generated by a sequencer, respectively. A precharge signal supplied to the X decoder is generated when the sequencer start signal is applied to the sequencer, or when the more significant bit portion of the address supplied to the X decoder changes or is incremented. Therefore, even when the less significant bit portion of the address supplied to the Y decoder changes or is incremented, the precharge signal supplied to the X decoder is not generated if the more significant bit portion of the address supplied to the X decoder does not change. Thus, the number of the precharge/discharge is reduced, and accordingly, the operating current of the dynamic logic circuit is decreased.

REFERENCES:
patent: 4660171 (1987-04-01), Modre et al.
patent: 4661724 (1987-04-01), Remington et al.
patent: 4817054 (1989-03-01), Banersee et al.
patent: 4896300 (1990-01-01), Shinagawa et al.
patent: 4910466 (1990-03-01), Kiuchi et al.
patent: 5059828 (1991-10-01), Tanagawa
patent: 5062082 (1991-10-01), Choi
patent: 5155705 (1992-10-01), Goto et al.

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