Dynamic logic circuit

Details Dynamic logic circuit Dynamic logic circuit

1999-02-25

2001-07-17

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S201000

Reexamination Certificate

active

06262615

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to logic circuits and more particularly to dynamic logic circuits.
As is known in the art, storage of data is required in many applications. One such storage circuit is a first-in first-out (FIFO) circuit. The FIFO circuit is commonly used for varying, or controlling, the delay, or latency, between data fed to an input of the FIFO and the data read from the FIFO. This latency control is important in synchronizing stages in, for example, a pipe-line operation.
FIG. 1
shows a bus architecture, or system
10
comprising a stage
0
driver
100
and a stage
1
FIFO storage section
110
. The driver
100
is here a CMOS driver, here an inverter having a pair of CMOS transistors
101
,
102
arranged as shown. The driver
100
is used to drive a bus RWD to the FIFO storage section
110
for data on the RWD. The data is transferred to the output line DQ after a certain latency. More particularly, transistor
101
is a p-channel MOSFET having its source connected to a +2.1 volt supply, its gate connected to a logic input signal fed to line
103
, and a drain connected to the source of n-channel MOSFET
102
. The gate of MOSFET
102
is also connected to line
103
, the drain of MOSFET
102
being connected to a reference potential, here ground. The logic input signal fed to line
103
varies between ground (i.e., a logic 0, here “low”) and +2.1 volts (i.e., a logic 1, here “high”). The transistor
102
has a threshold level, here 0.6 volts. Thus, when the logic input signal is logic 0, the output of the inverter. i.e., a read-write-drive (RWD) bus, becomes 2.1 volts and, on the other hand, when the input logic signal is logic 1, the bus RWD becomes 0 volts. It is noted that, in this example, the RWD bus is approximately 6mm long, which is resistive (approximately 200 ohms) and capacitive (approximately 5pF). The stage
1
FIFO includes a storage section
110
. The storage section includes a plurality of, here
3
, parallel storage units or registers,
110
1
-
110
3
, as indicated. Each one of the storage registers,
110
1
-
110
3
is identical in construction, an exemplary one thereof, here register
110
1
, being shown in detail. Each one of the registers
110
1
14
110
3
is fed by a pair of strobe pulses on lines: PNTi
1
, PNTo
1
; PNTi
2
, PNTo
2
; and PNTi
3
, PNTo
3
, respectively, as indicated. The lines PNTi
1
, PNTi
2
, and PNTi
3
, are sometimes referred to as pointer input lines. The lines PNTo
1
, PNTo
2
, and PNTo
3
, are sometimes referred to as pointer output lines. The voltage swing of the strobe pulses PNTi
1
, PNTo
1
; PNTi
2
, PNTo
2
; and PNTi
3
, PNTo
3
are here from 0 volts (i.e., a “low”, or logic 0) to +2.1 volts (i.e., a “high” or logic 1)
Thus, considering exemplary register
110
1
, such register
110
1
, includes an input CMOS transfer, or transmission, gate
120
, an output CMOS transmission gate
140
, and a latch
130
coupled between the input CMOS transmission gate
120
and the output CMOS transmission gate
140
, as indicated. The input CMOS transmission gate
120
includes an n-channel MOSFET
121
and a p-channel MOSFET
123
having their gates connected to the PNTi
1
line; the gate of MOSFET
123
being connected to such PNTi
1
line through an inverter, as indicated. The sources of MOSFET
121
,
123
are connected in common to the RWD bus. The latch
130
includes a pair of inverter connected in a conventional manner, as indicated. The output CMOS transmission gate
140
includes an n-channel MOSFET
141
and a p-channel MOSFET
143
having their gates connected to the PNTo
1
line; the gate of MOSFET
143
being connected to such PNTo
1
line through an inverter, as indicated. The sources of MOSFET
141
,
143
are connected in common to the output of the latch
130
and the drains are connected to data-output line DQ, as indicated. Thus, the output of the output CMOS transmission gate
140
appears on line DQ.
In operation, consider that the FIFO storage section
110
operates with control signal being supplied by a master clock, not shown, which produces clock pulses, CLK, shown in FIG.
2
A. Next, let it be assumed that strobe pulses are supplied to PNTi
1
, PNTi
2
, PNTi
3
, in response to a sequence of three consecutive clock pulses CLK, as shown in
FIGS. 2B
,
2
C and
2
D, respectively. In such example, the first logic input signal on line
103
is driven by the bus CMOS driver
100
and will pass through input transmission gate
120
in response to the strobe pulse PNTi
1
and will become latched into latch
130
. The second logic input signal on line
103
become latched in register
110
2
in response to the strobe pulse PNTi
2
. In like manner, the third logic input signal on line
103
will become latched in register
1
103
in response to the strobe pulse PNTi
3
. In order for the FIFO
10
to operate as a FIFO, the data in register
10
, (i.e., the first logic input signal) must be read out on line DQ prior to the subsequent PNTi
1
, which allows the register
111
1
, to fetch the subsequent data on the RWD bus again. Thus, in this example, the strobe pulse on line PNTo
1
must occur during the time of the strobe pulse PNTi
2
, as shown in
FIG. 2E
or during the time of the strobe pulse PNTi
3
, as shown in FIG.
2
F. That is, in order to prevent the latched data in a register from being destroyed, the latched data must be transferred out of the register before new data is latched into the same register. Thus, each logic input signal (i.e., data) has either a one, or two, clock pulse latency in the example with three registers to prevent the data from being destroyed. Considering the more general case of a FIFO having N registers, where N is an integer greater than 1, the latency may be from 1 to (N−1) clock pulses. Thus, by varying this latency from 1 to (N−1), the synchronization for following stages, not shown, can be optimized in a pipe-line operation.
The data stored in the latch of the registers
110
1
,
110
2
, or
110
3
, is transferred to data-output when the pointer output PNTo
1
, PNTo
2
, PNTo
3
, respectively, opens the CMOS output transmission gate
140
. The low voltage RWD signalling reduces a current of the driver
100
, while improving a data rate of the signalling. This concept is increasingly important for current and future VLSI. It should be noted that this FIFO
10
requires a level conversion from low voltage-swing RWD bus to the high-voltage FIFO to use the low-voltage signally concept. This voltage level conversion, however, requires additional logic which reduces the speed, and increases the design space of, the FIFO
10
.
As is also known in the art, dynamic logic circuits are becoming used in applications requiring speeds greater than that obtainable with CMOS type (i.e., static) logic, such as that described above in connection with FIG.
1
. Unlike static logic, dynamic logic circuits store data as charge. Thus, in order to operate properly, a node of the dynamic logic circuit must be pre-charged prior to responding to the logic state of an input signal to the dynamic logic circuit.
SUMMARY OF THE INVENTION
In accordance with the invention, a circuit is provided having: a storage circuit adapted to store data after such circuit has been placed in a set condition; an output circuit responsive to an output strobe pulse for coupling the stored data to an output; and, a reset circuit for resetting the storage circuit in response to a trailing edge of the output strobe pulse.
With such an arrangement, a low voltage bus signalling architecture is provided which enables incorporation of a bus driver having only NMOS transistors and a dynamic logic circuit.
In accordance with another embodiment, a circuit is provided having a charging circuit for placing an initial charge on a node. The circuit includes a data transfer circuit, responsive to an input data and the input strobe pulse, for transferring the input data to the node. Also provided is an output circuit, responsive to an output strobe pulse, for coupling th

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