Dynamic logic array with isolation and latching means between pl

Details Dynamic logic array with isolation and latching means between pl Dynamic logic array with isolation and latching means between pl

1988-02-10

1989-03-14

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307465, 307469, 34082591, H03K 19177, H03K 19096

Patent

active

048126853

ABSTRACT:
A dynamic logic array circuit can operate in two clock phases. It includes two matrices (1, 2) comprising dynamic logical gates, which require a precharging phase that precedes a functional phase. The array also includes memorizing means (7), the inputs of which are connected to the outputs of the first matrix (1) via first controlled isolating means (8), the outputs (MEO) of the memorizing means being connected to the inputs of the second matrix (2) via second controlled isolating means (9), the first isolating means (8) being controlled for authorizing the transfer of the signals emitted by the first matrix (1) to the memorizing means (7) during the precharging phase (PHO) of the second matrix (2) and the second isolating means (9) being controlled for authorizing the transfer of the data contained in the memorizing means (7) to the second matrix (2) during the precharging phase (PH1) of the first matrix (1). The invention is particularly applicable to CMOS technology. It can be used to make programmable or programmed logic arrays used in particular in computer control units.

REFERENCES:
patent: 4577190 (1986-03-01), Law
patent: 4611133 (1986-09-01), Peterson et al.
patent: 4661728 (1987-04-01), Kashimura
patent: 4661922 (1987-04-01), Thierbach
patent: 4740721 (1988-04-01), Chung et al.
patent: 4760290 (1988-07-01), Martinez
patent: 4769562 (1988-09-01), Ghisio

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