Pulse or digital communications – Cable systems and components
Reexamination Certificate
1999-10-22
2004-05-04
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Cable systems and components
C333S012000
Reexamination Certificate
active
06731687
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to bidirectional, differential, high speed serial data links, and more particularly, to a line balancing scheme for such data links.
2. Background Information
The Universal Serial Bus (USB) is a cable bus that supports data exchange between a host computer (USB host) and a wide range of simultaneously accessible peripherals (USB devices). The USB physical interconnect is a tiered star topology. A hub is at the center of each star. Each wire segment is a point-to-point connection between the USB host and a hub or a USB device, or a hub connected to another hub or USB device. The USB host contains host controllers that provide access to the USB devices in the system.
FIG. 1
shows a schematic view of the USB architecture. For more detailed information on USB, the reader is invited to review the “Universal Serial Bus Specification—Version 1.1” published Sep. 23, 1998.
A new, high speed mode being defined for USB can be classified as a bi-directional, differential, high speed, serial data link. One characteristic of bi-directional, differential, high speed, serial data links is that data packets are separated by intervals of “silence” where signals are not being transmitted on the data link. In such links, there is an inherent conflict between two opposing goals. On the one hand it is desirable to maintain a DC voltage balance between the two conductors which form the link in order to achieve the highest possible signal noise margin during transmission. However, on the other hand, having the lines at the same voltage during transmission of packets can potentially lead to unwanted noise pick up or oscillation in the receivers during silent intervals.
In the prior art, attempts to solve this problem were to permanently apply a DC voltage offset onto the two signaling lines. While the DC voltage offset reduces unwanted noise pick up and oscillation, the voltage offset causes reduced noise margin in the data link.
Another solution is the inclusion of a hysteresis loop in the receivers with the hysteresis window greater than the peak noise. Once again, although this reduces noise pick up and oscillation in the receivers, the noise margin is reduced.
In yet another prior art approach, the receivers are disabled during inter-packet transmission times. This approach is effective, but presents the problem of having to enable the receiver when the transmitter is about to transmit. In tightly timed systems this is possible, but in systems with loose or indeterminate timing, this is difficult.
Thus, what is needed is a method and apparatus for increasing the noise margin in a serial data link while reducing unwanted noise pick up and oscillation in the receivers.
SUMMARY OF THE INVENTION
A method for dynamically balancing a serial data link is disclosed. The serial data link includes a first transmission line and a second transmission line. The method includes the steps of creating a DC offset voltage between the first and second transmission lines when the serial data link is in an idle state. When the serial data link is in use to carry data, the DC offset voltage between the first and second transmission lines is removed.
REFERENCES:
patent: 6124727 (2000-09-01), Bridgewater, Jr. et al.
patent: 6304923 (2001-10-01), Klein
patent: 6308215 (2001-10-01), Kolbet et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Bocure Tesfaldet
Burd Kevin M
Intel Corporation
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