Dynamic latch circuit for preventing short-circuit current from

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307452, 307481, 307279, 307517, 377 28, 377 79, H03K 519, H03K 19007, H03K 19096

Patent

active

049202820

ABSTRACT:
Described herein is a dynamic latch circuit having a pair of control terminals connected to receive complementary first and second control clock pulses which are generated at a predetermined frequency, and a register section for detecting the voltage of an input signal, in response to each of the first and second control clock pulses, and generating an output signal from a capacitive output node which is charged or discharged in accordance with the voltage of the input signal and is subsequently set at a low potential or a high potential. The latch circuit further comprises a voltage-generating circuit for detecting, based on a period of time elapsed from the trailing edge of the last generated first control clock pulse, that the supply of the first control clock pulses has been stopped and fixedly setting the output node at the low potential.

REFERENCES:
patent: 3749936 (1973-07-01), Bell
patent: 3906258 (1975-09-01), Moe
patent: 4467285 (1984-08-01), Rinaldi
patent: 4598214 (1986-07-01), Sexton
patent: 4633097 (1986-12-01), DeWitt
patent: 4686386 (1987-08-01), Tatao

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