Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With contact or metallization configuration to reduce...
Patent
1991-08-28
1993-05-04
James, Andrew J.
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With contact or metallization configuration to reduce...
257508, 257736, 257776, H01L 2348, H01L 2946, H01L 2954
Patent
active
052084809
ABSTRACT:
A dynamic latch circuit which is fabricated in a semiconductor integrated circuit comprises a first circuit such as a clocked inverter and a second circuit such as an inverter. The first and second circuits are connected by a holding line. In the semiconductor integrated circuit, at least three interconnection layers are provided on a semiconductor substrate to be insulated by insulating layers, such that the holding line is provided as the secondly highest interconnection layer, and an output line of the second circuit is provided as the uppermost interconnection layer to be positioned on the straight upper side of the holding line. For this structure, a coupling capacitance which is formed between the holding line and a through line connected to a third circuit and provided as the uppermost interconnection layer is decreased.
REFERENCES:
patent: 4814841 (1989-03-01), Masuoka et al.
patent: 4857987 (1989-08-01), Ognda et al.
patent: 4974049 (1990-11-01), Sneda et al.
patent: 5045725 (1991-09-01), Sasaki et al.
patent: 5063433 (1991-11-01), Matsuo et al.
James Andrew J.
NEC Corporation
Ngo Ngan Van
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