Dynamic input stage biasing for low quiescent current...

Details Dynamic input stage biasing for low quiescent current... Dynamic input stage biasing for low quiescent current...

2001-05-01

2003-01-21

Nappi, Robert E. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S275000, C323S285000, C330S290000, C330S296000, C330S130000

Reexamination Certificate

active

06509722

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to amplifier circuits for use in regulator circuits and other applications, and more particularly relates to amplifiers having dynamic input stage biasing for minimized quiescent current operation.
BACKGROUND OF THE INVENTION
Regulator circuits are well known for providing a specified and constant output voltage or current from a poorly defined and often fluctuating input voltage or current. The regulation and control of supply voltage, particularly under changing load conditions, is perhaps one of the most fundamental and critical requirements of any electronic system design. For this reason, monolithic voltage regulator or power control circuits are considered to be among the essential building blocks of any analog or digital system.
FIG. 1
illustrates a simplified block diagram depicting a conventional linear series regulator circuit
100
. With reference to
FIG. 1
, the basic series regulator is a feedback circuit comprised of three primary sub-circuits, namely, a reference voltage generator
102
, an error amplifier
104
and a pass element
106
. The reference voltage generator
102
generates a reference voltage V
R
that is substantially independent of both the unregulated supply voltage V
IN
to which the reference voltage generator is connected, and temperature variations. The error amplifier
104
compares the reference voltage V
R
with a measured voltage V
S
which represents a scaled version of a regulated output voltage V
O
of the regulator. This scaled voltage V
S
is typically derived from a simple tapped resistive divider, for example comprised of resistors R
1
and R
2
connected in series across the output V
O
. Error amplifier
104
generates an error output signal at node
108
which is coupled to the pass element
106
for regulating a voltage drop across the pass element
106
such that the scaled voltage V
S
is held substantially equal to the reference voltage V
R
. A more detailed discussion of regulator circuit fundamentals is presented, for example, in the text A. B. Grebene,
Bipolar and MOS Analog Integrated Circuit Design
, John Wiley & Sons, pp. 481-514 (1984), which is incorporated herein by reference.
In many conventional regulator implementations, a high-current p-channel metal-oxide-semiconductor (PMOS) transistor device (not shown) is employed as the series-pass element
106
. The gate terminal of the PMOS device, in this instance, is coupled to the output of the error amplifier, the source terminal of the PMOS device is coupled to the unregulated input V
IN
and the drain terminal of the PMOS device forms the regulated output node V
O
. The resistance of the PMOS device, and hence the voltage drop across the device, is controlled by the error output signal generated by the error amplifier
104
to regulate the output voltage V
O
as stated above.
For very low output current levels, the loop bandwidth of a feedback circuit is primarily dominated by a large external capacitance C
BYP
. (and equivalent series resistance R
ESR
), which is typically on the order of one microfarad (1 &mgr;F), and an effective output resistance R
O
of the regulator. The combination of C
BYP
and R
O
results in a pole being formed which creates a 3-dB rolloff in the range of several hertz or less. The resulting rapid rolloff of gain at higher frequencies can significantly degrade certain performance characteristics of the regulator, such as, for example, ripple rejection (which is a measure of the regulator's ability to reject periodic fluctuations of rectified ac voltage signals at the input of the regulator).
For sensitive integrated circuit applications, such as, for example, voltage-controlled oscillators (VCOs) and radio frequency (RF) circuits typically found in cellular telephones, amplifier-based linear regulators must provide efficiently regulated output voltages while supplying output currents that can vary by five or six orders of magnitude, or more. A fundamental objective in such applications is that of providing stable and fast regulator performance over this wide dynamic load current range. Furthermore, it is desirable to provide such stability and response while dissipating a minimum quiescent current when little or no load current is being drawn.
Various techniques and circuit arrangements have been conventionally employed in an attempt to solve the above problems, including, for example, dynamic source/emitter biasing at the output stage of the error amplifier, specifying tight restrictions on output capacitor size and equivalent series resistance (R
ESR
) associated with the output capacitor C
BYP
, incorporating multiple amplifiers in the regulating/feedback path to handle dc and ac signal paths, and increasing feedback amplifier quiescent current to improve stability and dynamic response. These conventional approaches to solving the above problems, however, typically require more quiescent current, higher cost components, and/or more silicon area, all resulting in poorer overall performance.
Accordingly, there exists a need for an amplifier circuit, for use in regulator circuits and other applications, that is capable of providing superior stability and dynamic response across a full range of load current and load capacitance values, while dissipating a minimized quiescent current during low output current operation.
SUMMARY OF THE INVENTION
The present invention provides an amplifier, for use in regulator circuits and other applications, which dissipates a minimized quiescent current at low output current operation while providing enhanced stability and dynamic response across a wide range of load currents and load capacitance values. The invention employs a dynamic input stage biasing architecture, whereby input stage bias current is operatively controlled as a function of output load current, thereby increasing the bandwidth of the amplifier as load current increases. In this manner, parasitic poles associated with the amplifier are pushed out in frequency so as not to compromise amplifier stability, particularly at low output load current levels, as the dominant pole formed by the amplifier output impedance and output bypass capacitance increases with increased load current.
In accordance with one aspect of the invention, an amplifier having dynamic input stage biasing includes an input stage operatively coupled to an input of the amplifier. A controlled current source is coupled to the input stage and is responsive to a control signal for at least partially controlling an input bias current generated by the controlled current source. The amplifier further includes a sense circuit which is operatively connected in a feedback arrangement between an output of the amplifier and the controlled current source. The sense circuit measures an output load current from the amplifier and generates the control signal in response thereto. In this manner, the input bias current, as well as the amplifier bandwidth, is a function of the output load current of the amplifier.
These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 5939867 (1999-08-01), Capici et al.
patent: 6046640 (2000-04-01), Brunner
patent: 6157176 (2000-12-01), Pulvirenti et al.
patent: 6246221 (2001-06-01), Xi
A.B. Grebene, “Bipolar and MOS Analog Integrated Circuit Design,” John Wiley & Sons, pp. 481-514, 1984.

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