Dynamic flow instruction cache memory organized around trace seg

Details Dynamic flow instruction cache memory organized around trace seg Dynamic flow instruction cache memory organized around trace seg

1994-03-30

1995-01-10

Harrell, Robert B.

Boots, shoes, and leggings

395400, 395425, 36496422, 36496424, 36496426, 364DIG2, G06F 938

Patent

active

053815335

ABSTRACT:
An improved cache and organization particularly suitable for superscalar architectures. The cache is organized around trace segments of running programs rather than an organization based on memory addresses. A single access to the cache memory may cross virtual address line boundaries. Branch prediction is integrally incorporated into the cache array permitting the crossing of branch boundaries with a single access.

REFERENCES:
patent: 5136687 (1992-08-01), Johnson
patent: 5136696 (1992-08-01), Beckwith et al.
Minagawa et al., "Pre-decoding Mechanism for Superscalar Architecture," IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, May 9-10, 1991, pp. 21-24.
Mike Johnson, Superscalar Microprocessor Design, 1991, pp. xxi-xxiv and 57-85.
Ray Weiss, "Third-Generation RIEC Processors," EDN, Mar. 30, 1992, vol. 37, No. 7, p. 96(10).
William Stallinga, "Reduced Instruction Set Computer Architecture," Proceedings of the IEEE, Jan. 1988, vol. 76, No. 1, pp. 38-55.
Oehler et al., "IBM RISC System/6000: Architecture and Performance," IEEE Micro, Jun. 1991, pp. 14-17 and 56-62.
Smith et al, "Boosting Beyond Static Scheduling in a Superscalar Processor," Proceedings of the 17th Annual International Symposium on Computer Architecture, IEEE, May 28-31, 1990, pp. 344-354.

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