Dynamic flip-flop with static reset

Details Dynamic flip-flop with static reset Dynamic flip-flop with static reset

1984-02-09

1986-12-23

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, 307445, 307269, H03K 3284, H03K 1756

Patent

active

046314202

ABSTRACT:
A D-type flip-flop (10) receives the D input on an input line (14) of a transfer gate (12) that also receives the flip-flop clock signal. A state gate (20) forwards the transmission-gate output when the signals on two of its input lines (22) and (24) remain true. To reset the flip-flop asynchronously, a false signal is imposed on one of the input lines (22) of the state gate (20). By coordination of a second clock signal, which is applied to a second transmission gate (34), with the reset signal, the reset condition is held until the next clock pulse on the first transmission gate (12). The flip-flop ordinarily operates as a dynamic circuit, but, in order to maintain the reset condition in circumstances in which the reset state is to be maintained for an extended period of time, a latch gate (26) is enabled by a true signal on one of its input lines (32) to feed the reset output of the state gate 20 to one of its input terminals (24 ) so as to latch the flip-flop in the reset state.

REFERENCES:
patent: 3739193 (1973-06-01), Pryor
patent: 3812384 (1974-05-01), Skorup
patent: 3993916 (1976-11-01), Copeland, III et al.
patent: 4114052 (1978-09-01), Manabe et al.
patent: 4181862 (1980-01-01), Dingwall
patent: 4492927 (1985-01-01), Holberg
patent: 4495628 (1985-01-01), Zasio

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