Dynamic FIFO for simulation

Details Dynamic FIFO for simulation Dynamic FIFO for simulation

2008-03-18

2008-03-18

Rodriguez, Paul (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S019000, C703S022000, C716S030000

Reexamination Certificate

active

07346483

ABSTRACT:
To perform a simulation, a design can be divided into “blocks” described by models. To ensure that data is efficiently transferred from an source model to a destination model, a dynamic first-in first-out (FIFO) can be placed between these models. The initial size of the dynamic FIFO can be set to a relatively small value. To prevent deadlock, the size of the FIFO can be automatically increased in size by increments. In this manner, the memory resources of the FIFO can be tightly controlled. Advantageously, the size of the optimized dynamic FIFO can be used as the desired size of the FIFO implemented in silicon, thereby also ensuring efficient use of silicon resources.

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Clifford E. Cummings, Peter Alfke “Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons” SNUG-2002 San Jose Ca. pp. 1-18.

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