Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2003-03-20
2004-09-21
Goudreau, George A. (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S715000, C438S009000, C216S059000, C216S067000
Reexamination Certificate
active
06794302
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to plasma reactor processes including dry etching processes and more particularly to a temperature control methodology for dynamically adjusting wafer temperature zone parameters in a plasma etching process to achieve critical dimension (CD) uniformity.
BACKGROUND OF THE INVENTION
In the field of plasma (dry) etching, various processing parameters including, for example, RF power, RF bias, pressure, gas flow rate, temperature, and vacuum conditions are predetermined in order to accomplish a particular plasma etching process. In addition, many plasma etching processes are preprogrammed to follow a series of steps for predetermined time periods also referred to as a process recipe, where the processing parameters may be altered at each step to achieve a desired etching result.
While there are several types of plasma reactor configurations including a wide variety of gaseous reactants used for etching a semiconductor wafer to form semiconductor features, some etching processes are mores susceptible to wafer temperature than others. For example the temperature of the process wafer determines the rate of chemical reactions that take place on the wafer surface in an etching process including deposition and etching away of polymers in etching high aspect ratio features including for example, openings as well as protrusions. For example, the wafer temperature may affect the etching rate, especially in reaction controlled processes. Temperature control of a semiconductor wafer during an etching process is becoming increasingly critical as semiconductor feature sizes decrease and the diameter of process wafers increases. For example, it is frequently required to achieve a critical dimension etching uniformity of less than about 3 nm in some processes, for example in gate etching to adequately control gate length which critically affects electrical function of the transistor.
For example, where the etch reaction is the dominant removal process. Since the etch reaction is affected by the wafer temperature, local gradients in the wafer temperature may result in differing etching rates thereby resulting in different critical dimension uniformity over the wafer surface. Other etching processes may be dominated by the recombination of gas species, for example including chlorine atoms may be strongly influenced by the wafer temperature.
Since process wafers are frequently heated during etching, for example from a backside by an electrostatic chuck including a heating means, the wafer temperature may vary over a diameter of the wafer due to radial heat transfer. Thus, critical dimension (CD) non-uniformities caused by temperature variations of the semiconductor wafer may vary concentrically from wafer center to edge. Etching non-uniformities including edge to edge non-uniformities also referred to as a leveling effect adversely affect subsequent photolithographic processes by causing defocusing difficulties in transferring mask images to the wafer surface.
A device sizes, including transistors are scaled down to below about 1 micron, CD requirements have become more stringent and difficult to control. For example, two parameters known as bias and tolerance are frequently used to define CD requirements in the semiconductor processing art. CD Bias is the difference in lateral dimension between the etched image and the mask image. CD uniformity is a measure of the statistical distribution, for example 3× sigma, of CD bias values that characterized the uniformity of etching. For example, in etching polysilicon gate structures, the gate length determines the channel length and the acceptable electronic functioning of a transistor making gate CD uniformity critical in the gate formation process. Nonuniform etching rates over the diameter of the process wafer are frequently strongly influenced by the temperature of the process wafer may adversely affect the manufacture of the transistor device in several ways. For example, wafer edge-to-edge (across wafer diameter) variations in etching rates cause CD non-uniformities within the wafer, for example concentrically, which contribute to defocus in subsequent photolithographic processes. As a result, the etching non-uniformities compound CD bias in subsequent process steps. A goal in the semiconductor manufacture process industry is to achieve CD uniformity to within less than about 30 Angstroms.
A problem in prior art etching processes and systems is the limitation of carrying out etching processes by trial and error. Since a plasma etching process is frequently a multi-step process to etch through a series of different material layers, it is frequently difficult to determine after the fact which etching process was a major contributor to the CD non-uniformity. Further, CD inspection is frequently accomplished after the etching process is complete causing a waste of time and resources if the CD uniformity is not within specifications. Frequently, temperature control adjustment in a plasma etching process is a ‘black art’ limited by trial and error techniques to obtain the desired CD uniformity. Changes in one of several components of the plasma reactor system over time may unpredictably change heat transfer characteristics and consequently wafer process temperatures including gas pressures and gas flow rates which also must be frequently adjusted to maintain CD uniformity. Further, etching parameters are frequently required to be altered from one etching process to another, making the re-establishment of optimal etching parameters including optimal gas flow characteristics time consuming and frequently limited to reliance on a trial and error approach.
Thus, there is a need in the semiconductor processing art to develop an improved wafer temperature control methodology for in a plasma etching process to compensate for CD non-uniformity and achieve repeatable and predictable CD uniformity.
It is therefore an object of the invention to provide an improved wafer temperature control methodology for in a plasma etching process to compensate for CD non-uniformity and achieve repeatable and predictable CD uniformity while overcoming other shortcomings and deficiencies of the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for compensating for CD variations across a semiconductor process wafer surface in a plasma etching process.
In a first embodiment, the method includes providing a semiconductor wafer having a process surface comprising patterned features; carrying out a first plasma etching process wherein the semiconductor wafer is heated according to at least two selectively controllable temperature zones; determining a first dimensional variation of etched features with respect to reference dimensions over predetermined areas of the process surface including the at least two selectively controllable temperature zones; determining operating temperatures for the at least two selectively controllable temperature zones to achieve a targeted dimensional variation change in the first dimensional variation to achieve a desired second dimensional variation in a subsequent etching process; plasma etching the process surface according to the desired operating temperatures; and, determining an actual dimensional variation change for use in at least one subsequent plasma etching process.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.
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Chang Ming-Ching
Chen Li-Shiun
Chiu Yung-Hog
Lin Huan-Just
Lin Li-Te S.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Assocaites
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