Dynamic divider circuit

Details Dynamic divider circuit Dynamic divider circuit

1973-10-19

1983-07-19

Anagnos, Larry N.

Electrical pulse counters, pulse dividers, or shift registers: c

Phased clocking

Field-effect transistor

307452, 307481, 377117, H03K 2322, H03K 19096

Patent

active

043945864

ABSTRACT:
A dynamic divider circuit comprised of insulating gate field effect transistors and capable of operation using minimal current consumption in a reduced space is provided. Master and slave multiple inverters and an intermediate inverter are formed from complementary connected P-channel and N-channel insulated gate field effect transistors, the master and the slave inverter being directly coupled to the master inverter. The coupling of the master, intermediate, and slave inverters providing reduced current consumption and a more simplified circuit by utilizing the parasitic capacitance of said field effect transistors as a memory.

REFERENCES:
patent: 3431433 (1969-03-01), Ball et al.
patent: 3483400 (1969-12-01), Washizuka et al.
patent: 3560998 (1971-02-01), Walton
patent: 3710271 (1973-01-01), Putman
patent: 3716723 (1973-02-01), Heuner
patent: 3737673 (1973-06-01), Suzuki
patent: 3745371 (1973-07-01), Suzuki
patent: 3749937 (1973-07-01), Rogers
patent: 3757510 (1973-09-01), Dill
patent: 3823551 (1974-07-01), Riehl
patent: 3829713 (1974-08-01), Canning
patent: 3833822 (1974-09-01), Carbrey
Suzuki et al., "Clocked MOS Calculator Circuitry"; IEEE Internat'l Solid-State Circuits Conference; Session VI: LSI Components, 2/14/1973.

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