Dynamic divider circuit

Details Dynamic divider circuit Dynamic divider circuit

1975-07-08

1977-12-13

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

H03K 2308

Patent

active

040631141

ABSTRACT:
A dynamic divider circuit for dividing a clock signal by n-1 where n is an odd integer is provided. The divider circuit includes n -series connected C-MOS inverter circuits, the output of the last of the series-connected inverter circuits being coupled to the input of the first of the series-connected inverter circuits to define a closed loop. n-1 inverter circuits include first switching circuits coupled thereto, the remaining inverter circuit having a second switching circuit coupled thereto, each of the switching circuits being adapted to receive the clock pulse to be divided and produce at the output of each of the C-MOS inverter circuits the divided clock signal.

REFERENCES:
patent: 3749937 (1973-07-01), Rogers
patent: 3829713 (1974-08-01), Canning
"Codymos Freq. Dividers Achieve Low Power Consumption and High Freq." by Oguey et al., Electronic Letters, vol. 9, No. 17, 8/23/73.

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