Dynamic disable mechanism for a memory management unit

Details Dynamic disable mechanism for a memory management unit Dynamic disable mechanism for a memory management unit

1987-09-18

1989-12-19

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1200, G06F 1300

Patent

active

048886882

ABSTRACT:
In a data processing system comprising a central processing unit (CPU), a memory management unit (MMU) and a storage system, the MMU translates each of the logical addresses output by the CPU to a corresponding physical address in the storage system by selectively using translation descriptors stored in an address translation cache. In response to receiving a dynamic disable signal, the MMU will provide each logical address as the corresponding physical address without translation. In addition, the MMU will preserve the state of the entries in the address translation cache, and "freeze" the translation activities.

REFERENCES:
patent: 4736290 (1988-04-01), McCallion
patent: 4737909 (1988-04-01), Harada
patent: 4740889 (1988-04-01), Motersole et al.
patent: 4763244 (1988-08-01), Moyer et al.
patent: 4774652 (1988-09-01), Dhuey et al.

Affiliated with

Also associated with

Rating

Dynamic disable mechanism for a memory management unit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic disable mechanism for a memory management unit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic disable mechanism for a memory management unit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1906602