Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
1999-05-10
2001-05-22
Yoo, Do Hyun (Department: 2185)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S189050, C365S189070, C365S203000, C365S204000, C711S108000, C711S128000
Reexamination Certificate
active
06236585
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is circuits for addressing content addressable memories.
BACKGROUND OF THE INVENTION
This invention relates to a content addressable memory circuit architecture with unique features. Content addressable memories are referred to as CAMs for brevity and are widely used in conjunction with cache RAM to provide additional features in high performance memories found in present day microprocessors. CAM functional elements are typically loaded with special words representing address, data, or instructions, entries for which the processor might need to do a later search or identity comparison.
The data stored in CAMs are accessed based on their contents, rather than their address. This functionality is useful in many applications, including databases, table look-up, and associative computing. Particularly, the processor might need to know if any special words previously stored in a CAM is identical to a word which the processor holds under consideration for a processor decision. One specific example of CAM usage would be address-protection applications. While CAM functions normally test for completely identical words (words identical in every bit position) it is desirable in address protection applications to have a variable-entry-length feature. This relates to the structure of the CAM as follows. Content addressable memories which have only the completely-identical-word test feature use a single valid-bit storage latch per word location. One digital state of this bit signifies that the word was written by the processor on a previous processor operation and that the entire word qualifies for the identity check.
SUMMARY OF THE INVENTION
The content addressable memories of this invention have a variable-entry-length test feature having two bits stored in all locations, one bit of the entry word, and one valid bit. Each entry bit of these locations in the CAM can hold data which can be labeled valid when the valid bit is set “high” or “invalid” when the valid bit is set “low”. Thus, as an example, a 32-bit address, stored in one CAM word location can be tested for identical content at, say only 6 bit locations, rather than all 32 bit locations by merely setting the companion valid bits “high” at the desired 6 locations and “low” at all other locations. This enables the computer operating system to allocate variable-size memory ranges for different processes, which results in improved application performance.
One object of this invention is to provide an improved CAM circuit architecture which allows an entry, including a data bit plus a valid bit, to be stored at each bit entry location of each CAM word. This allows realization of variable entry-length of any length.
Another object of this invention is to provide for the use of completely dynamic evaluation logic, which gives enhanced performance.
Another object of this invention is to improve performance of the dynamic evaluation logic further by employing low V
T
transistors (LVT) in speed-critical areas of the circuit, while providing protection against additional leakage current flow which could result if such devices were used indiscriminately.
Yet another object of this invention is to precharge the dynamic gate in the CAM cell with data, thus eliminating the distribution of a clock signal inside the CAM. This helps to alleviate crosstalk and noise problems and reduces circuit routing congestion.
These and other objects are accomplished in accordance with the present invention in which a CAM cell having both a data latch and a valid latch. These latches have dual rail input data (sdata and {overscore (sdata)}) and dual rail input valid (svalid and {overscore (svalid)}) signals. The CAM cell also has input from WE (write enable) and dual rail dynamic inputs addr and {overscore (addr)} which supply an address, or match word, to the word under consideration.
When a particular word is addressed with the dual rail dynamic address signals, addr and {overscore (addr)} becoming active, a match
i
signal is generated which signifies a match if match
i
is “high” or no match if match
i
is “low”.
In the circuit configuration provided by the present invention, the addr and {overscore (addr)} signals are applied to the CAM cell in such a way that allows for the use of low V
T
(LVT) transistors in the speed critical portion of the circuit.
In addition the combination of dynamic logic with attendant significant reduction in circuit capacitance, and low V
T
transistors with attendant faster turn-on time and higher drive current together provide the optimum circuit performance.
By precharging the address lines, addr andaddr, to a “low” state, clock distribution within the CAM array can be eliminated. This significantly simplifies circuit routing and also results in lower crosstalk and noise.
Including both the data latch and the valid latch in each CAM entry location provides for variable-entry-length and attendant improved system performance.
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Brady III W. James
Kim Hong
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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