Dynamic control of power management circuitry

Details Dynamic control of power management circuitry Dynamic control of power management circuitry

1997-06-03

1999-06-08

Miska, Vit

Horology: time measuring systems or devices

Electrical time base

Solid state oscillating circuit type

364707, 395750, G04F 500, G06F 100

Patent

active

059109300

ABSTRACT:
Method and apparatus for dynamic control of power management circuitry in a microprocessor. A clock and power management subsystem within the microprocessor contains clock generation and control logic and a powered-down mode register. The register is controlled by register control logic in the microprocessor and determines the powered-down mode of the various hardware units that make up the microprocessor. The clock generation and control logic also receives a powered-down mode enable signal from each of the hardware units. The hardware unit receive a re-power-up signal which, when activated and deactivated, can cause the hardware units to de-activate and activate, respectively, the powered-down mode enable signal. This combination of features allows continuous, repetitive, dynamic, hardware-controlled entry into exit from power saving modes without software intervention, thereby allowing the power saving modes to be used more often and more effectively for shorter periods of time than would be possible with software controlled power management.

REFERENCES:
patent: 5392437 (1995-02-01), Matter et al.
patent: 5502689 (1996-03-01), Peterson et al.
patent: 5511203 (1996-04-01), Wiser et al.
patent: 5630143 (1997-05-01), Maher et al.
patent: 5634131 (1997-05-01), Matter et al.
patent: 5664205 (1997-09-01), O'Brien et al.
patent: 5715467 (1998-02-01), Jirgal

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