Dynamic control of configurable logic

Details Dynamic control of configurable logic Dynamic control of configurable logic

1993-03-19

1994-05-31

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307468, H03K 19173, H03K 19094

Patent

active

053172124

ABSTRACT:
A method and device for performing logic functions. A logic array (1) is controlled by a plurality of DRAM cells (101). The DRAM cells are, in preferred embodiments, loaded in a serial fashion with a shift register (1205). Refresh according to one aspect of the invention utilizes a shift register (1201) with a circulating "0." A charge pump circuit, voltage boost circuit, and a variety of memory cell/logic array configurations are also disclosed.

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Foss et al., "Peripheral Circuits for One-Transistor Cell MOS RAM's," IEEE Journal of Solid-State Circuits, vol. SC-10, No. 5, Oct. 1975.
Engineering Course in MOS Technology, American Microsystems, Inc., 1970.
Foss et al., Design Analysis and Comparison of Silicon Gate 4K RAMs, Feb. 1976, Section 5.

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