Dynamic content addressable memory device and a method of operat

Details Dynamic content addressable memory device and a method of operat Dynamic content addressable memory device and a method of operat

1992-10-27

1994-06-07

Popek, Joseph A.

Static information storage and retrieval

Associative memories

Ferroelectric cell

365222, 365200, G11C 1500

Patent

active

053195892

ABSTRACT:
A bit line control circuit is disclosed for implementing a dynamic content addressable memory. The bit line control circuit includes a read circuit 12 and a first write circuit 13 connected to data line pairs DT, /DT, a sense amplifier 14, a bit line discharge circuit 15, a bit line charge circuit 16, a transfer gate circuit 17, and a second write circuit 18. The bit line control circuit is connected to a CAM cell array through bit lines BLa, /BLa. Various operations such as write, read, refresh and match detection and the like necessary in the dynamic associative memory can be implemented under simple timing control by a simple circuit configuration.

REFERENCES:
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patent: 4975873 (1990-12-01), Nakabayashi et al.
patent: 4991136 (1991-02-01), Mihara
patent: 5130945 (1992-07-01), Hamamoto et al.
"A 30-kbit Associative Memory LSI for Artificial Intelligence Machines", by Takeshi Ogura et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 4, Aug. 1989, pp. 1014-1020.
"A 288-kbit Fully Parallel Content Addressable Memory Using Stacked Capacitor Cell Structure", by Tadato Yamagata et al., IEEE 1991 Custom Integrated Circuits Conference, pp. 10-13.
"A Bit Line Control Circuit Scheme and Redundancy Technique for High-density Dynamic Content Addressable Memories", by Tadato Yamagata et al., ICD91-142, pp. 59-66 (Nov. 22, 1991).

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